Filtering the ambient noise caused by PSU

By Dr. Min Zhang, the EMC Consultant

One of the questions people often asked is “how do I filter the noise coming from the PSU in my pre-compliance test set-up?”

This is a typical issue in our pre-compliance set-up, especially the power supply unit (PSU) we use is often designed for EMC testing. They will provide a stable output voltage, but the output voltage contain a high level of conduced RF current, both in differential and common mode.

You can always use an EMC tent with filter on the tent wall. But even with a tent, you might still need to add some filter on your PSU. Here we give you some practical tips in dealing with the noise generated by PSU.

Most of the PSU in the market has isolated topology (such as flyback), which means the conducted noise is shown on both input and output sides. For this reason, we propose the following filter configuration in a pre-compliance set-up.

As it can be seen, on the mains cable, since the Live, Neutral and PE wires are inside one cable bundle, we can only apply a common mode filter by using a two-turn ferrite. Depending on the PSU, sometimes, you might need a two-turn 75 ferrite and a two-turn 31 material to give you the optimal filtering on the mains. Note, this also reduces the noise on the DC output significantly.

On the DC output, follow the same principle. However, since we have the output lines separate, we can apply a differential mode filter by using a two-turn or three-turn 75 material ferrite. This essentially forms an inductor and should work with the output capacitor of the PSU and the input capacitor of the LISN as part of a C-L-C pi filter.

The input capacitors on the LISN should be configured according to

By having this configuration, you should expect a relatively clean ambient noise on your LISN output.

TEM Cell for Radiated Emissions

by Dr. Min Zhang, the EMC Consultant

This article compares the TEM Cell results (near-field) against antenna measurement (far field).

A detailed video demonstration can be found in

Some details with regards to the test set-up.

  1. The TEM Cell unit we used is Tekbox TBTC-3, a large TEM cell compared with other TEM cells. This TEM cell has a spectrum height of 15cm, which is suitable for many units, especially PCBs.
  2. The TEM Cell is located inside an EMC shielding tent, this is desirable as for radiated emissions, an open TEM Cell will pick up ambient noise.
  3. The effective area inside the TEM cell is defined by the standard, the DUT needs to be placed inside the defined area within the TEM Cell.
  4. The insulation support is very important, here, we used 5cm tall insulation support and we made sure that the wires are placed on the insulation support.
  5. The wire length is chosen to be more or less the same as what the standard defines, i.e. in this case, between 1.5 and 2m. However, due to the constraint of the space, the wires are meandered, this would affect the radiation profile.

The following diagrams compared the TEM Cell results with that of the far field measurement (according to CISPR 25, 1 meter antenna location to the DUT).

A second DUT is tested.

Second DUT tested in the TEM Cell

The comparison results are shown below.

The TEM Cell result shows a very similar radiated emission profile with the comparison of antenna far field result, the noise level in the lower frequency range shows about 8 dB less

This might be explained by the fact that the DUT has also less conducted noise compared with the benchmark unit. See below:

Conducted emission results between the DUT and the benchmark unit

If the conducted emission level in the DUT is 8 dB less, it explains why the radiated emission level of the DUT is also lower than the benchmark unit.

Overall, the TEM Cell result shows a very similar noise profile compared with the far field measurement. We are confident to use this method as a pre-compliance test set-up.

Grounding and Shielding in Instrumentation – A Space Project Study

By Dr. Min Zhang, the EMC Consultant

Grounding and shielding has always been a challenging issue when it comes to large system installations. Even the most experienced engineers in prestigious companies often get the system installation wrong, intentionally or unintentionally.

In this article, we discuss the grounding and shielding techniques using a practical case study. In this case, the system under the discussion is an instrumentation system used for a space project. The ground loop created by the ground wires lead to loop issues, several solutions are discussed to address this issue.

The system

For demonstration purposes, we can treat the DUT as a pure resistive load, the signal needs to be measured is the voltage across the receiving load RX. The load is ‘grounded’ to the facility clean ground. Note that there is an X symbol at the bottom of the RX, the X symbol represents the ‘star’ point, a reference point often used in space application (As a satellite floats in the space, there cannot a ‘ground’ point, hence the ‘star’ point from historical reasons).

For minimal noise voltage received by RX, all three conductors (DC+ line, DC- line and the shield) should ideally have zero RF voltage difference with regards to the ‘star’ point X. Wire bonding strap S1 and S2 are crucial to ‘close the field’ inside the shield. It has been found that the shield also needs to be connected to the ‘star’ point via a ground wire strap S3 to ensure V3=0.

The Instrumentation System

Noise introduced by the Ground Loop

Due to the parasitic capacitance between the V+ and the inner shield (C1) and the parasitic capacitance between the V- and the inner shield (C2), RF noise voltages are developed, therefore V1,2 are not zero. This is particularly true when the connection between the PSU and the EUT is long.

The DUT is powered by tens of DC power supplies, all of which are galvanically isolated from the metal racks. However, the internal assembly of the power supply unit (PSU) represents significant parasitic capacitance C3 with regards to the rack frame, typically 50 nF per unit. In case where the rack frame is connected to the primary power supply ground, the residual noise marked PN of the three-phase current imbalance will be transferred to the DUT line via C3.

Demonstration of a worst-case scenario : Shield end S1 is not connected to the ‘star’ point, ground strap S3 is also disconnected. Rack chassis is earthed to the power ground via ground strap S6. Pink line is the ground loop.

It is easy to break the loop, isn’t it?

It looks easy to break the loop by disconnecting S6. In order to achieve a ‘clean’ break, we also need to make sure the earth wire is cut. Note that special preventions are required to comply with personnel safety requirements. But this disconnection is not a clean break from RF noise point of view. Because the power supply unit has an input filter which includes Y capacitors to earth. These capacitors now provide the noise path as shown below:

Ground loop noise uses the low impedance path provided by C3
This is another ground loop

We therefore need to further break the loop, this can be achieved by the following configuration. Breaking the connection between the ‘star’ point and the facility clean ground is the key, because now the ‘star’ point X is the same ground potential as the power ground, so there is a very small potential difference between the two ground points, this will prevent current from using C3. The ground strap S4 is important to achieve minimum potential difference between the two ground points.

The minimum grounding scheme which limits the ground loop current

The proposed solution provides the minimum configuration for such an instrumentation. The grounding scheme can be further improved by the following optimum configuration. The key component in this configuration is the mains isolation transformer unit which consists of two shields. The double shielded transformer is specially made for best attenuation of primary-to-secondary noise transfer, i.e. transfer capacitance C4 is mined to <10nF.

The optimum grounding scheme

HV safety cannot be overlooked

By Dr. Min Zhang, the EMC consultant

One of my frequently visited websites is the UK government product safety alerts, reports and recalls website. Link is provided here .

A quick browse on the website, you will find lots of recalled products due to safety failures. Among which, the high voltage (HV) safety failures have taken a large proportion of the total cases. What is more interesting is that the number of the hair care products shown in the list. It is quite concerning if we find a “good hair day” turns into a nightmare due to the safety issues. I have friends who experienced leakage current issue with a counterfeit hair dryer product and I will not be surprised if some of these products could cause fire.

One of the products that have HV safety issues

The products that are forced to be recalled often present serious risks of electric shock. These products often either do not meet the requirements of the Electrical Equipment (Safety) Regulations 2016 or the plugs & Sockets (Safety) Regulations 1994 (BS1363). Some common failure modes are summarised:

  1. Failure to comply with the creepage and clearance requirements (including poor quality soldering).
  2. The wire diameter is too thin, i.e. not rated for the suitable current.
  3. Wrong/no fuse is fitted.
  4. Lack of general safety design, for instance, lack of power interrupting mechanism.
  5. Insufficient insulation.
I have seen some HV design in the past which pose serious health and safety hazards

If the safety operation of these products cannot be guaranteed, I cannot imagine if they have done any EMC tests. Yet, some of these products have a CE marking label. We should not allow products like this appear in the market.

Many of these products are imported from Asia into the EU market, and some of them are even sold in big platforms such as Amazon, the Range and TKMAXX. Clearly this shows a sign of lack of expertise in quality control within these organisations.

Using electrolytic caps to dampen the system

By Dr. Min Zhang, the EMC consultant

Sometimes, the larger ESR of an electrolytic capacitor is not a bad thing. In certain applications, we need to have some resistive components to provide damping of the system. A typical example is presented here.

Resonance is often seen in a system that is caused by input cable inductance and the input ceramic capacitors (which generally have very small ESR value). One effective way of preventing this from happening is to add an electrolytic capacitor in between. The ESR of the electrolytic capacitor makes the system more stable. An example is simulated below, where there is a two-meter cable between the voltage source and the circuit. We simulated two scenarios, one without the electrolytic capacitor and one with. The step response shows that the system is damped by the electrolytic capacitor.  

Simulation of an electrolytic capacitor’s damping capability

Filter Layout

by Dr. Min Zhang, the EMC Consultant

Mach One Design EMC Solutions

Here is a classic question; – where should we put the filter with regard to the noise source? Shall we place the filter close to the noise source or away from it? The answer is; – if you can, you should always place the filter in a quiet environment, i.e. away from the noise source. 

Here we should not get confused with what we say about ‘solving EMI problems at the noise source’. We all know that the best approach to solving EMI problems is to suppress the noise source. Without understanding the principles, engineers often put an EMI filter close to the noise side, such as a SMPS on a PCB, or a line filter close to a motor drive circuit. This creates problems because the strong leakage field of the noise source will couple strongly with the passive components of a filter. As a result, a carefully designed filter, which is supposed to give 60-80 dB attenuation according to the simulation/calculation, often ends up having only 10-20 dB insertion loss. This is particularly true when the frequency increases. 

The circuit shown in Figure 1 is given to demonstrate the point. The input stage of a typical buck converter using in integrated switching IC is shown. On the input side, the filter stage is separated from the input capacitors by including the red dashed line. Note that there can never be a strict separation line between the filter and the input capacitors as the input capacitors also provide a low impedance path to noise, so they work nicely with the filter. But here the two are separated to make the point.

Figure 1 The input stage of a typical integrated buck converter

The input capacitors are part of the SMPS design. Therefore, one will need to design the capacitors to make sure there is always enough energy delivered in the most efficient way whenever the switch is turned on. This is often achieved by the following: 

  1. Populate the input supply rail with several decoupling capacitor sizes (0402, 0603, 0805, etc) so that energy is available over a wide frequency spectrum.   
  2. The decoupling capacitors should be connected as close as possible to the Vin pin. 
  3. Locate the smallest size capacitor (in this case C1, 0402) first to the Vin pin.
  4. The electrolytic capacitor C4 serves as the main energy storage device, but it also provides damping of the system due to its relatively larger ESR.
  5. If the electrolytic capacitor has a metal housing, such as aluminium, due to the larger size of the electrolytic capacitor, the metal housing also serves as a shield to block some of the electric field created by the SMPS. 

The filter stage is designed as a multi-stage filter which consists of two inductors and a few ceramic capacitors. The red line shown in Figure 1 indicates that there must be a distance between the filter and the input capacitors. This is to avoid field coupling and make the input filter stage more effective. On a PCB level, this is often achieved through the following steps:

  1. Put the input filter away from the noise source, if the noise source is a SMPS and it is located on one side of the PCB, the safe side of a filter should be on the opposite side of a PCB.
  2. If the filter stage has to be on the same side of the SMPS, a physically long distance shall be kept. The distance depends on the strength of the leakage field of the SMPS. For instance, if the switch node of the SMPS is kept quiet by a shield, then the distance between the filter and SMPS can be shortened.
  3. The connection between the filter stage and the input capacitors should always be a high impedance path such as an inductor (L1 shown in Figure 1).

The same principle applies to much larger systems such as an industrial motor drive system or power supply. For instance, a line filter used for an industrial motor drive application such as the one shown in Figure 2 (a) is always much more effective if it is placed near the mains entry point of the cabinet, i.e. to keep the mains wiring and the line filter far away from other wiring and harnessing inside the cabinet. Again, the reason is to avoid close field coupling between the noise source and the filter component. 

Figure 2 (a) a line filter made by REO, (b) best location for such a filter to be effective


If you want to learn more about EMC and become an expert in troubleshooting EMI problems. Why not attend our video training course? Priced from $199, you can get 10 hour lessons. Check

Design Filters with Simulation

by Dr. Min Zhang, the EMC Consultant

Mach One Design Ltd

Most of the noise that engineers come across in the field is generated by high-frequency, fast switching devices. Typical examples are motor drive inverters, DC-DC converters, power supplies, microcontrollers and communication chips. Therefore, filters are often designed to suppress the noise caused by switching events. 

In the past, IGBTs and MOSFETs were the main switches. MOSFETs were predominantly used in low voltage applications while IGBTs were used in medium voltage applications. When the voltage is above 800V, IGCTs and GTOs are the devices of choice. MOSFETs can be switched rather quickly, but they are limited by the voltage rating and their thermal properties, therefore, typically they are limited to about 150kHz switching frequency and the rise time is often found to be from a few nanoseconds to 10s of nanoseconds. IGBTs have a tail-current, which limits their switching speed and switching frequency. Typically, the switching frequency of an IGBT based system is limited to about 60kHz. 

This will soon change as the newly developed wide-band-gap (WBG) devices such as Silicon-carbide (SiC) and Gallium-nitride (GaN) devices show superior performance over the MOSFETs and IGBTs. The fact that they can switch faster at higher voltage means the dV/dt of WBG devices is a lot higher. This inevitably leads to more EMI. 

There are two aspects of a switching event, the switching frequency and the switching speed. When talking about EMI associated with the switching events, many engineers often focus on the switching frequency and overlook the impact of switching speed. The switching speed should have more attention paid to as it is the main EMI source. It is not necessary to have a high switching frequency to cause EMI problems. Consider this example; an electrostatic discharge (ESD) event does not have MHz of switching frequency, but the rise time is as short as 10s-100s of picoseconds. One ESD event could potentially radiate the energy to a nearby system and cause trouble.

A switching event is simulated in the SPICE simulation software. The simulated switching event has a 60kHz switching frequency, with 600V DC voltage, and the duty ratio in this case is 50%. The rise time is set as 12 ns to give a 5V/ns switching speed. Spectrum analysis of the switching event is shown in Figure 1. 

Figure 1 Spectrum of a 60kHz switching event with a rise time of 5V/ns

Notice that the -20dB/decade line and the -40dB/decade line crosses at the frequency point of 1/πtrise, which in this case is calculated to be 26.5MHz. Ideally, one would like the -40dB/decade roll off to occur at a lower frequency point, because the noise spectrum decreases a lot faster after this crossing point. But the roll off point only depends on the rise time of a switching event. 

Engineers often don’t have the option of shifting this point. This is because the rise time of a switching event often cannot be increased as increased rise time leads to more switching loss and less system efficiency. 

To demonstrate the effect of sharp rise time, in Figure 2, a faster rise time (10V/ns) is simulated for comparison. As it can be seen, every time the switching speed is doubled, it results in a 3-6dB noise increase from 1/πtrise

Figure 2 10V/ns rise time spectrum (blue) vs 5V/ns rise time (green)

Once the spectrum characteristics of a switching event are understood, it is then easy to design a filter that aims to suppress the noise at the frequency range of interests. 

For instance, a motor drive causes conducted emission between 100 kHz to 10 MHz, the lower frequency range noise (<1MHz) often needs differential mode filtering, whereas, between 1MHz and 10 MHz, some form of common-mode filtering is needed. A three-phase filter that has sufficient attenuation in this range would be a good choice. One example is a C-L-C (π) filter, which is shown in Figure 3. 

Figure 3 REO CNW 103 three-phase filter gives good attenuation in the lower to mid frequency range


If you want to learn more about EMC and become an expert in troubleshooting EMI problems. Why not attend our video training course? Priced from $199, you can get 10 hour lessons. Check

Understanding Insertion Loss

by Dr. Min Zhang, the EMC Consultant

Mach One Design EMC Solutions

Filters are almost always a part of an electronics design. Design engineers design a filter to achieve certain attenuation in a specified frequency range. We have seen that with inductive components, the impedance increases with frequency while the capacitors’ impedance decreases with frequency. By combining inductors and capacitors, we can build many types of filters, such as high-pass, low-pass or band-pass. Popular filter configurations include L-C, C-L-C (π) or L-C-L (T).

The performance of a filter is measured in terms of attenuation, or insertion loss, both of which use the units of decibels (dB). The best place to start this discussion is CISPR 17, which defines the technical terms of a filter. It also presents a detailed explanation of how to measure the insertion loss of a filter. 

A filter often provides attenuation to noise in both differential mode and common mode. At a low frequency range (often between a few kHz and 1 MHz), noise is predominantly a differential mode mechanism. When the frequency goes up, common mode noise becomes more dominant. 

Take a 50Ω/50Ω (source impedance/load impedance) system for instance, CISPR 17 defines two tests to measure the filter performance, which are symmetrical (differential mode) and asymmetrical (common mode). The test set-ups are shown in Figure 1. The signal generator (G) performs a signal sweep between the defined frequency range. The voltage across the load (Z2) is measured during the sweep.

Figure 1 Test set-up for insertion loss, CISPR 17 (a) symmetrical test, (b) asymmetrical test

Note that in both cases Zand Z2 are 50 Ω. In reality, a 50Ω/50Ω system rarely exists. Therefore, the worst-case test set-ups, such as 0.1Ω/100Ω and 100Ω/0.1Ω give better filter performance analysis. 

The insertion loss is defined as 

Insertion Loss = 20log(V20/v2)

Where V20 is the voltage across Z2 before the filter is inserted, and V2 is the voltage measurement after the filter is inserted, as per Figure 2.

Figure 2 Test circuits for insertion loss measurement, CISPR 17 (a) reference, (b) filter

While it sounds easy and straight forward, engineers often need to see the test set-up to understand the concept better. Figure 3 shows the test set-up of an REO filter according to CISPR 17. The circuit diagram of the filter being tested is shown in Figure 4(a) and the insertion loss curve is shown in Figure 4(b). 

Figure 3 Test set-up for filter insertion loss
Figure 4 (a) Circuit diagram and (b) typical attenuation of a REO single phase mains filter

A simulated filter model is built in the SPICE simulation tool and the circuit can be found in Figure 5. As shown, when introducing parasitics into the simulation model, a close to real measurement result can be achieved. To build a useful simulation model, especially before the filter is implemented, engineers need to understand the parasitics of each passive component in the filter. If the passive components are arranged so that coupling occurs, engineers should also be aware that the filter performance could be compromised by coupling. If an off-the-shelf filter is purchased, it is a good idea to always ask the filter manufacturer for a measured attenuation curve such as the one shown in Figure 4. 

Figure 5 Simulation model shows a close-to-measurement attenuation curve


If you want to learn more about EMC and become an expert in troubleshooting EMI problems. Why not attend our video training course? Priced from $199, you can get 10 hour lessons. Check

Advanced Implementation of Ferrite Cores

by Dr. Min Zhang, the EMC Consultant

Mach One Design

One of the challenges with filters are the cost associated with high voltage and high current filter components. When the current rating exceeds 10s of amperes, the magnetic components become costly. 

One way of implementing a cost-effective filter is to utilise magnetic cores. The ferrite cores introduced previously are just one example. Of course, the core material could be nanocrystalline or others depending on the application. Figure 1 demonstrates this concept. A ferrite, together with Y-capacitors form an R-L-C filter for the common-mode noise. The great virtue of this configuration is that the core is not subjected to saturation, so it is suitable for high current application. 

Figure 1 A low-cost filter implementation using ferrite cores and Y-capacitors

Magnetic cores are seen in many applications, such as the DC-DC converter used in Tesla electric vehicle (shown in Figure 2). The output current for this type of application often reaches beyond hundreds of amperes, any inductors on the output would be bulky, heavy and costly. Instead of placing inductors, the positive and negative rails were put on adjacent layers of the board. Depending on the current rating, often wide track or plane were used. Similar to a bifilar winding, all the magnetic field then flows in the small gap between the two planes and the only remaining flux is the high frequency common mode noise. All one needs to do then is to put a core (or multiple cores) through the board or around the board. Mechanically, this is also easy to do. 

Figure 2 A DC-DC converter used in Tesla electric vehicles, multi-cores were clamped in the 12V DC output bus bar. The current rating of the output could be as high as 250 Amps


If you want to learn more about EMC and become an expert in troubleshooting EMI problems. Why not attend our video training course? Priced from $199, you can get 10 hour lessons. Check

The Magic Loop – Part 3

Techniques of using magnetic field loops

by Dr. Min Zhang, the EMC Consultant

Mach One Design



There are two ways of positioning a magnetic field loop over a PCB. When positioned horizontally to the PCB (shown in Figure 6 (a)), a magnetic field loop picks up the changing magnetic field using the whole loop area. This is what the EMC engineers called “sniffing”. The purpose is to identify the “hot” area (maximum changing magnetic field area) on the PCB. The magnetic field loop can be connected either to a spectrum analyzer or an oscilloscope with 50 ohm impedance. The “hot” area is identified when the results on the scope/spectrum analyzer shows maximum values during the “sniffing” exercise. 

When positioned perpendicularly to the PCB (shown in Figure 6 (b)), a magnetic field loop is used to measure the induced voltage on a particular trace/track on the PCB. The reason that the loop needs to be placed perpendicularly is to minimize the induced voltage on the side wires of the loop. In this case, the magnetic field loop should be connected to a high bandwidth oscilloscope as the measurement is in the time domain.

Figure 6 Positioning of a magnetic field loop over a PCB (a) horizontal position to “sniff” (b) perpendicular position to measure induced voltage on a trace


For a typical buck converter, the current waveforms of the switch side and the load side are shown in Figure 7.  Both the switch node and the “hot loop” area are shown. A Texas Instrument buck EVM board is used for demonstration purposes. 

Figure 7 The “hot loop” area in a buck converter

Moving a magnetic field loop horizontally over the PCB, one can easily identify the “hot loop” area. In Figure 8, the induced peak to peak voltage reached 300 mV for a small magnetic field loop, indicating a sharp rise time during the hard switching events. If one were to integrate the result, a current waveform similar to that is shown in Figure 7 (the MOSFET current waveform) can be arrived at. Remember, the magnetic field loop outputs a voltage reading (V=Mdi/dt). To get the current waveform, one need to do an integration. 


Figure 8 Placing a magnetic field loop horizontally over the PCB and move along the loop until the maximum induced voltage is seen in the oscilloscope 

Similarly, when placing the loop over the inductor, a smooth voltage waveform is seen as shown in Figure 9. Using the integration function in the oscilloscope, one can calculate the inductor current waveform (shown in green triangular waveform in Figure 9).

Figure 9 Placing the loop over the inductor gives the induced voltage caused by current going through the inductor. The integration of the waveform gives the inductor current waveform

After the “hot loop” area is identified, the next step is to place the magnetic field loop perpendicularly to the PCB and move it slowly across the suspicious area. Note down areas where large voltage spikes are seen during the exercise. Because the area on the PCB is rather small, a smaller size shielded loop is used instead.  A few areas on the PCB were probed, all showed similar induced voltage level as shown in Figure10. 

Figure 10 Use a smaller size loop and place it perpendicularly on the PCB, traces/tracks where large di/dt can thus be measured, the result is shown here. 

Can we predict the EMI results based on this technique?

This is basically asking if there is any correlation between the near-field measurement and far field measurement result. And the answer is no. Any attempt to use the near field measurement to predict far field performance would lead to either under-estimation or over-estimation. Thus the proposed technique in this article is most suited for a few scenarios listed below:

  1. If a product/system is known to have failed EMC test, using a magnetic field loop can quickly help locate the noise source and propagation mechanism.
  2. If a probe is well calibrated, then using the loop might give you a Pass/Fail indication. 

But how to calibrate a homemade magnetic field loop? Since each loop is made differently in size. For shielded magnetic field loops, the diameter of the coaxial also plays a role in affecting the mutual inductance. Many factors could affect the reading of a magnetic field loop. Therefore, the loop method result should only be treated as a qualitative indicator. 

One method the author often uses is to test the loop on a known product. For instance, both the conducted and radiated emission test results of the EVM board in this study were known to the author. Therefore, for products that need to pass the automotive EMI test standards such as those defined in CISPR 25, any induced voltage over 100 mV on a small magnetic field loop certainly will raise a red flag. If the product is a home appliance product, then even 200mV induced on the same loop will most likely be okay. 


[1]       D. C. Smith, High Frequency Measurements and Noise in Electronic Circuits, New York: Van Nostrand Reinhold, 1993. 

[2]       Doug Smith, Arturo Mediano, “Shielded vs unshielded square magnetic field loops for EMI/ESD Design and Troubleshooting,” InCompliance Magazine, vol. July, no. July, 2014.