Emissions from logic circuits are dominated by switching edges which exhibit a fast rise/fall time (note that this is not the same as transition time and is rarely specified in data sheets; where it is, it is usually a maximum figure). Fast edges are generally regarded as a good thing for functionality, but are a handicap for EMC. Where parts of the circuit must operate at high speed, use fast logic only for those purposes.

The main source of radiation in digital circuits is the processor clock (or other system clocks) and its harmonics. All the energy in these signals is concentrated at spot frequencies. Since the radiated emissions standards do not distinguish between narrowband and broadband, these narrowband emissions should be minimized first.

The graph shows the measured harmonics of a 2.5MHz clock for three devices of different logic families in the same circuit. Note the emphasis in the harmonics above 200MHz for the 74AC and 74FC types. It's precisely this frequency range which calls for serious effort in layout and shielding. Radiation of such emissions is caused by the di/dt (changing current) flowing either in the PCB traces or in connected cables. For a faster rise time with a given circuit capacitance, the driver output current di/dt must be increased: more current is needed to charge or discharge the capacitance. The efficiency of these routes is proportional to F or F² and so emphasizes the higher frequency content.

It is preferable to minimise the distribution of clocks around a board or system, and this means that if possible they should remain local to their point of use. If they must be distributed, this should be done in such a way as to minimise coupling from the clock lines; balanced differential pair transmission (even over short distances) is good for this, and the receiving end should be matched and/or buffered to prevent reflections and minimise the energy carried on the long lines.

The choice of fundamental clock frequency is also important. The lower the better, as this reduces the high frequency energy content in direct proportion. There may be particular frequencies (including harmonic multiples and intermodulation products) to be avoided in the system or in other nearby systems, or particularly tight limits over a given range mandated by the emissions specification. A useful tool for emissions diagnostics, particularly in complex systems with several clocks, is a spreadsheet which records all harmonics and intermodulation products within the spectrum of interest.

Once the clocks have been sorted out, you then need to pay attention to other broadband sources, especially data/address buses and backplanes, and video or high-speed data links. The least significant data/address bit usually has the highest frequency component of a bus and should be run closest to its ground return. Because backplanes carry all buses and clocks in the system, and carry a heavy capacitive loading, they should always use a multilayer board with a ground plane, and daughter board connectors should have a ground pin next to every clock or data pin.

Clock and bus buffering

Noise is induced on the supply rails by the switching action of each logic gate in the circuit. As each gate changes state, a current pulse is taken from the supply pins because of the different device currents required in each state, the external loading, the transient caused by charging or discharging the node capacitance, and the conduction overlap in the totem-pole output stage. The supply current spike causes a disturbance in both the supply voltage and the 0V line, because of the inductive impedance of the lines. The voltage developed across an inductor is

V          =          -L · di/dt

Pulses on a high-impedance 0V line can exceed the noise threshold and cause spurious switching of innocent gates, as well as being responsible for emissions coupled out of the circuit. This phenomenon is known as "ground bounce" and its cures are well documented in order to achieve signal integrity: principally they involve use of a continuous ground plane and associated power planes on the board.

The supply pin current pulse is magnified in synchronous systems when several gates switch simultaneously. A typical example is an octal bus buffer or latch whose data changes from #FFH to #00H. If all outputs are heavily loaded a formidable pulse - exceeding an amp in fast systems - will pass through the supply pins. Ground noise on a microprocessor board can be observed by probing a wide-bandwidth oscilloscope between two points on the ground line.

To control the amplitude of the high frequency edges of this supply noise, an increase in the output impedance of the driver device is necessary. This is achieved by a series component, either a resistor or a ferrite chip impeder, at the driver output, acting in concert with the node capacitance. Of course, this limits the rise and fall times of the signal and its value is a compromise; in critically-timed circuits its value must be chosen carefully. But if the timing requirements can be relaxed, it should be included as a matter of course in any emissions-significant lines, clock or data.

The following example illustrates 'ground bounce' in a high-speed digital system. 'Ground bounce' occurs due to the ground level difference between TX ground and RX ground of two microcontrollers. High-current pulses on the ground can cause 'ground bounce,' leading to temporary common-mode changes in the clock signal. ESD protection diodes such as TVS can help suppress the amplitude of the common-mode voltage, but they cannot eliminate the noise(as they have a clamping voltage). The differential swing of the clock signal could be affected if the level of common-mode voltage change exceeds the specified input level of the clock receiver.

Spread spectrum clocking

One alternative way to reduce the amplitude of clock frequencies and their harmonics is to deliberately spread their occupied bandwidth, by means of frequency modulation (FM). As the diagram shows, by extending the occupied bandwidth beyond the measurement bandwidth, there will be effectively a reduction in the measured amplitude, even though the energy being emitted hasn't changed. As the harmonic multiple increases, so does the degree of improvement gained in peak amplitude, since the energy is spread over a wider bandwidth. This gives an easy way to reduce clock harmonic emissions with no circuit or layout changes other than implementing the modulation in the clock generator - sometimes known as a "dithered clock oscillator". The modulation waveform which gives the most even distribution of energy across the spreading range (the "Hershey kiss") has been patented; several manufacturers offer clock chips that include this as a standard feature. The effect of frequency modulating a control clock (typically at around 30kHz) is to increase clock jitter and so for some applications with critical timing, or with a phase-locked loop (PLL) downstream of the modulated clock, the technique is unacceptable. It is not necessary to centre the spreading spectrum on the clock frequency; down-spreading or up-spreading are possible and what is chosen will depend on the digital timing characteristics.

It's a controversial technique since although it takes advantage of a characteristic of the test methods, there is disagreement as to whether it actually reduces the interference potential of a product. It has been likened to "getting rid of a cow pat by jumping on it".

Click here for Questions