Totem pole conduction current

When the output driver of a CMOS device changes state, there is a finite transition time while the gate input voltage is swinging in one direction and the output voltage is swinging in the other, during which both devices are on simultaneously. Thus a current flows from the positive to the negative supply pin irrespective of the degree of loading on the output pin. This is known as "totem-pole" or Δ-I conduction current. While the output sections are the most significant, since they have the largest silicon area, other CMOS drivers within the IC also contribute to this current. When the entire IC is synchronously operated from the same clock, all the switching edge currents add together at the same time.

The amplitude of the current is a function of the detailed design of the CMOS pair in each stage in the IC. Various IC design techniques can be used to ameliorate the effect, such as careful control of gate threshold voltage, or de-synchronising the clock edges in different sections of a VLSI device to "smear out" the resulting pulse. Some IC manufacturers are noticeably more adept at achieving low noise than others, even for the same circuit function and generic part number. Even so, supply pin noise cannot be eliminated and its effect on the emissions from the whole product must be controlled by decoupling.

Digital decoupling

No matter how good the VCC and 0V connections are, track distance will introduce an impedance which will create switching noise from the transient switching currents. The purpose of decoupling is to maintain a low dynamic impedance from the individual IC supply pin to 0V. This minimises the local supply voltage droop when a fast current pulse is taken from it. In general, the capacitor must be located close to the circuit it is decoupling in order to minimize the inductance of the current loop. The critical distance is less important when good, low impedance power and 0V planes are used, since the impedance contributed by the planes is to a first order non-inductive.

The crucial factor when selecting capacitor type for high-speed logic decoupling is lead and package inductance rather than absolute value. Minimum inductance offers a low impedance to fast pulses. The decoupling components need to be tailored to different frequency ranges as their parasitic inductances become significant: bulk (electrolytic or high-value ceramic) capacitors cover the low frequency range up to 3MHz, individual smaller chip capacitors cover the HF range up to 30MHz, and power/ground planes reduce the impedance above 30MHz as chip capacitor inductance becomes important. At frequencies of several hundred MHz depending on size, the power/ground plane pairs become resonant as a low impedance transmission line.

Placement

The "rules" for decoupling are by no means universal: they depend on the method chosen for power distribution on each rail, specifically on whether or not power planes are used (assuming a ground plane is always used), and on the separation distance of the planes. Multi-layer boards with 6 or more layers and power/ground plane pairs on adjacent layers can be regarded as closely spaced. In this case, the placement of a decoupling capacitor has little to do with the inductance of its connection to an active device. But with wider spacing, or if individual traces are used to distribute power, the connection inductance between the device power pins and the capacitor must be minimized, so both placement and tracking have to be carefully considered. In summary:

Choose the capacitor first for low inductance, then for maximum capacitance

Locate the capacitor to minimise the effect of total loop inductance:

Boards without power planes: – one local decoupling capacitor per active device, connected between the power and ground pins of the active device

Boards with closely spaced power planes: – location of capacitors is not critical, use the largest capacitance available in a small package size, and use as many as possible distributed around the board

Boards with power planes spaced > 0.5mm: – location of capacitors is critical, locate them next to the power/ground pins of each device and use the largest capacitance available in a small package size

The above breakdown is based on a more detailed article by Todd Hubing.

Modelling the decoupling strategy

The decoupling strategy for a particular power distribution rail can quite easily and usefully be modelled with a simple circuit simulation package. The impedance versus frequency between the power and ground planes can be calculated and particular resonances can be explored. The contributory factors are

the bulk decoupling capacitance, its ESR and parasitic inductance

the distributed HF decoupling capacitors, their ESR and parasitic inductance

inter-plane capacitance

the resistive loading of the power rail due to the supplied ICs

This method ignores transmission line effects which become significant when the largest electrical dimension (the physical dimension, multiplied by the square root of the dielectric constant, around 4.2 - 4.5 for fibreglass) of the plane approaches a quarter of a wavelength. To model these properly would need an electromagnetic simulator.

The impedance across the planes should be adequately low at any frequency at which significant energy will be injected, for instance at clock harmonics. “Adequately low” is hard to define, but 10 - 100mΩ is usually achievable and desirable. It is this impedance across which a radiating voltage will be developed by HF power supply currents.

The model here is derived from Altera's Power Distribution Network design tool.

Decoupling capacitor layout

The pad and via placement of plane decoupling capacitors has a direct influence on the overall inductance and hence the effect of the capacitor. To achieve the minimum inductance the vias should be as close as possible to each other and should be within the capacitor pads. This, of course, means tented vias, which increase the cost of the board. But you can achieve as good a result by taking a pair of vias outside the pad but directly adjacent to them and to each other, as shown opposite under "optimum without tented vias". On the other hand, there should never be a reason to lay out capacitors with extended traces to their vias as shown at the top left of the diagram.

The proximity of the vias to each other makes use of their mutual inductance to decrease the overall inductance of the loop, since the current in one via mirrors and partially cancels that in the other. To keep the loop impedance down even further, it should be as short as possible in the vertical direction: that is, the planes should be on the next layers underneath the capacitor pads.

The same principles apply to layout of EMC-related capacitors which are not used as power rail decoupling; examples are interface filters and RF connections to chassis.

Analogue circuit decoupling

While the above has concentrated on decoupling digital circuits for control of Δ-I currents, there is an equally important role for decoupling in analogue circuits. Here the issue is not so much noise emissions from HF power supply currents drawn by the active circuits. Instead, the purpose is to prevent HF power rail noise from affecting the operation of the devices due to their less-than-perfect power supply rejection. There are two principal factors:

externally-coupled RF and transient interference appearing across the power rails and creating demodulation or disruption in the ICs;

an unacceptably high impedance across the power rails which leads to spurious oscillation or instability in wideband amplifiers.

For both reasons, high frequency decoupling is necessary for all analogue circuits, following the same principles as described above for digital circuits.

Adding a small capacitor Cin, usually a few tens of picofarads, across the + and - inputs of an opamp can improve its RFI immunity, with the caveat that the effect of the capacitor on the gain and phase margin of the circuit should be checked.

Power rail decoupling is more important than one would think for analog ICs like op amps. Even low-frequency op amps need high-quality power & Gnd decoupling to prevent the op amp from breaking into oscillation at a much higher frequency than the unity gain bandwidth of the device. When designing op amp circuits, even low-frequency ones, be sure to provide decoupling capacitors right at the power pins, making as small a loop as possible between the + and - power pins. The purpose of Cds in this case is to decouple the stray inductance introduced by trace/track connections on the PCB. If you have a solid ground plane, and short connections to the power rail, then Cds are less important.

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