By comparison with the gridded ground, the lowest ground impedance is when an infinite variety of parallel paths are provided and the ground conductor is continuous, and it is then known as a ground plane. This is easy to realise with a multilayer board and offers the lowest possible ground path inductance. It is essential for RF circuits and digital circuits with high clock speeds. The usual multilayer configuration also includes the power supply rail as a separate plane, which provides a low distributed source impedance for high frequency power supply currents. It also enables the designer to create a defined characteristic impedance for signal tracks.

The ground plane will reduce mutual inductance coupling between circuits by ensuring that the coupled current loops are not co-planar. Capacitive coupling between tracks will not be directly affected by the ground plane, but it does provide a useful capacitive shielding effect between adjacent boards.

A plane conductor is a useful tool in EMC because its impedance is much less than that of a linear conductor. A plane of infinite extent has no inductance: the impedance from any point to any other is determined simply by resistance. With a finite plane, the edges create discontinuities along which fringe magnetic fields generate inductance. At the centre of the plane, inductance is still zero, but it rises as the edges are approached. This partial inductance appears as an impedance within the total circuit loop that includes the plane and of course a voltage is developed across it when current flows. Its effect can still be reduced by bringing the rest of the circuit very close to the plane and so maximizing the mutual inductance of the two halves of the loop.

The actual resistance (as opposed to inductance) of either an infinite or finite plane does increase with frequency, due to the skin effect (which also has an impact on shielding properties). The magnetic fields within the conductor force the current flow towards the surface, resulting in less bulk conductor available to it and hence an increase in the apparent resistance. The skin depth  is that distance from the surface of the conductor at which the current density has reduced by 1/e or 8.6dB.

Breaks in the ground plane

Now imagine a large but not infinite ground (0V) plane with circuits on it carrying high frequency currents. One of these circuits crosses a slot that has been cut into the plane. For circuits that don't cross the slot, the return current path can stay close to the signal path, giving minimum enclosed area and minimum return path impedance. But for the circuit that crosses the slot, the return current is forced away from the signal path, increasing the total loop area and reducing the mutual inductance between the two halves of the path. The effect of this is to inject unwanted self-inductance L_G into the 0V return current path, which since V = -L_G·di/dt, causes a noise voltage V_N to be developed across the offending 0V segment. This then translates into noise emissions (di/dt from intentional circuit currents) or susceptibility (di/dt induced by external fields or applied voltages), since once a noise voltage appears across different regions of the 0V rail, it cannot be filtered out or otherwise removed: the whole 0V structure becomes contaminated. At the same time, this voltage appears across the two parts of the plane, each of which has a high capacitance to the environment due to its surface area, and so forms an efficient radiating dipole.

The resulting rule is simple: never deliberately put slots or apertures in the ground structure. If for practical reasons slots are unavoidable, the second rule is never run high frequency signals across them. This applies equally to PCB ground planes and to cables running along chassis structures - and for the same reason.

"Moats" in PCB ground planes are a particular danger and should preferably not be used, or should only be used if no critical circuit tracks cross them.  If slots are necessary, critical tracks should be routed around the edge of the slot rather than directly across it. Large numbers of vias can create a slot in a multilayer construction and they should be broken into smaller groups to allow current flow in the plane between them.

Not all of the copper area of a complete ground plane needs to be used: a partial ground plane (that doesn't cover the whole board) is also acceptable, though its edges remain the weakest regions. At high frequencies, return current will flow preferentially in the neighbourhood of its signal trace. This is because such a route encloses the least area and hence has the lowest overall inductance. The advantage of an overall ground plane is that the optimum return path is always available, allowing the circuit to achieve minimum radiating loop area by its own devices. For this to happen, it is essential that the plane remains unbroken in the direction of current flow. No matter how much copper there is on the board, it is not a ground plane if it creates a large loop for return currents.

DGND + AGND vs. overall GND

Unfortunately, a common cause for split ground planes is designers’ enthusiasm to keep analogue and digital 0V planes separate. There is a perfectly good reason for this: particularly with sensitive and wideband analogue circuits, the digital currents flowing in the DGND section may be sufficient to produce enough ground noise to “infect” the analogue circuit. For instance, 1mA flowing at 10MHz in a ground plane which might have an impedance at this frequency of 0.02 will generate a ground noise voltage of 20µV; this is approaching the resolution of a standard 16-bit A-D converter and could easily be responsible for jitter in the least significant bit.

This problem is avoided if the two circuit 0Vs are kept separate with a single-point connection between them, so that currents in one cannot flow in the other. Such a solution is often advised by the manufacturers of mixed-signal ICs. But although it is a simple enough solution by itself, it runs into problems when more than one connection is needed because of multiple ADCs on a single board, and it invariably worsens the external EMC – RF emissions and immunity – of the system, because of the dipole effect of the two 0V segments. Also, the break between the planes prevents a local return path for any signals which need to be carried across from one plane to the other, such as digital-to-analogue control lines. Such signals must either all be carried across the link between the planes, underneath the ADC, or they will be exposed to induced interference between the planes.

A further problem is that, with more than one plane, there then becomes a choice between which of these to bond to the chassis or other metalwork of the product. With a single universal 0V plane, all points of fixing of the PCB can be used to give multiple ground bonds, which makes the whole assembly electrically “rigid”. But this cannot be done when you have more than one plane; you have to decide which of them should be referenced to the chassis, and invariably there are competing demands which cannot be resolved easily.

The problem of multiple planes becomes much more complicated if there is more than one ADC or similar device. In this case, to follow the simple advice of separate planes with a single point connection either leads to many different analogue 0V planes, each electrically separate from each other, which is usually hard to realise from the system point of view, not to mention the power supplies; or to one analogue 0V plane, with a single point connection across one of the ADCs, which leaves the other devices exposed to interference between their digital and analogue ground connections; or to multiple connections between the analogue 0V and digital 0V planes, under each ADC, which defeats the purpose of having separate ground planes.

All these problems are resolved if a single 0V plane is maintained for both digital and analogue sections. No ADC device is left exposed to interference across its ground pins, and no choice has to be made about which 0V to connect to chassis or how to isolate analogue and digital power supplies. Control signals between analogue and digital sections are protected by proximity to the plane along their entire route. There is no dipole structure for external RF coupling.

This approach doesn’t absolutely prevent intermixing of analogue and digital ground currents on the PCB. So it is vital to observe segmentation between the circuits as if there actually was a ground plane split, so that there is no unintended path by which digital supply currents could pass through the analogue section. It is also helpful to buffer control signals that pass from the digital section to the analogue with resistors to attenuate any unwanted HF noise they may carry.

Equally important is the need to exercise a strict discipline in the ground routing of the most sensitive sections to avoid common impedance coupling; so that any ground noise that remains – the ground noise will spread more across the plane at lower frequencies, where the beneficial effect of mutual inductance to the signal path is lacking – is not introduced into the signal circuit; differential analogue inputs are a helpful means of ensuring this.

The power plane

As discussed in the section on layer stack-up, power planes have to be adjacent to a ground plane in a multilayer board in order to enjoy a high capacitance and therefore good decoupling properties. The capacitance between the two planes is easily calculated from their overlapping surface area A cm², the spacing d cm between them and the dielectric constant ε_r of the board material:

C          =          0.0885 · ε_r · A/d pF                    (1)

But they don’t have to follow the ground plane outline exactly and indeed it’s better if they do not.

A large area of power plane, such as if an entire board is supplied from a single V_CC supply plane, lowers the resonant frequency of the power/ground plane physical structure to the point where it can become troublesome. Separating a large plane into individual smaller planes, each with its own decoupling capacitors and supplied via an isolating series choke, pushes these resonances typically into the GHz region where they are more lossy and generally less harmful. It also reduces cross-coupling via the power plane of different circuits on the board, and reduces the spread of V_CC noise across the board. The series chokes - for instance, surface mount ferrites - need only have a few tens of ohms impedance in the VHF range to be effective at segregating the individual planes. The segregation boundaries should follow natural divisions in the circuit structure as far as possible.

This segmentation approach is not appropriate for ground planes, which should be continuous over the whole PCB.

Power plane resonance

The mention above of resonances in the power/ground plane structure has echoes of the three-dimensional enclosure resonance discussed elsewhere. In this case, it's two-dimensional, and a resonance will occur between the two planes when the distance in either axis is a half wavelength, or multiples of that. The presence of dielectric between the planes reduces the electrical dimension by a factor of the square root of ε_r. So the lowest resonant frequency will occur at

F          =          15000/(d · √ε_r)                    (2)

where F is in MHz and d is the largest distance in cm across the plane structure

It's not as simple as this, as the presence of decoupling capacitors (which are invariably inductive, being above self-resonance) detunes the resonance, so an exact calculation of the frequency is rarely successful; to get a more accurate idea you would need to employ an electromagnetic wave simulation. The effect of resonances is to create peaks in power distribution network impedance around the board, which in turn can lead to emissions or immunity problems at these frequencies. Making the geometry of the planes irregular rather than rectangular reduces the impact of the resonances and is generally good practice.

Edge effects and the 10·h rule

In the centre of a plane inductive effects are minimal, but towards the edges magnetic fields do not cancel and the inductive impedance of the plane rises. For this reason it is not advisable to locate noisy or sensitive components near the edge of the plane but to allow a rule of thumb distance of 10 times the layer thickness, at least, for such circuits (including their tracks) away from the edge. This rule should apply also to partial planes, that is those where there is a break in the plane layer within the board. The critical aspect is the edge of the plane, not the edge of the board.

It can also apply to power plane layers placed against a ground plane. If the power and ground planes were to have exactly equal edges, the transmission line formed by the two planes would be terminated in a sharp open circuit and the problem of transmission line resonances would be potentially severe. Staggering the edges of the planes softens the impedance mismatch and reduces the Q of the resonance.

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