The z-axis of the board has an important contribution towards its EMC performance. How you implement the layer stack depends on the number of layers you plan to put in the board.

One consequence of the dependence on layer separation is that the detail of the vertical sandwich construction of the PCB can be as important for its EMC as is the layout. The separation is determined by the thickness of the pre-preg and core materials used in the build of the bare board. If this is left to the PCB manufacturer and is not specified by the circuit designer, or anyone else, you end up with the default thicknesses used by a particular board supplier, which might be perfectly adequate for the EMC performance of the product and so is never questioned; but if another board supplier is chosen during the product life cycle, it is entirely possible that a different set of thicknesses could be used which result in changed performance. To guard against this, make sure that you specify layer thicknesses in the PCB drawing, if necessary checking with your preferred supplier what their defaults will be.

Transmission line layers

For high-speed circuits it will often be necessary to create one or more constant impedance layers. The geometry (track width and separation distance to an adjacent ground plane) of these layers has to be carefully controlled to determine the characteristic impedance Z₀ of transmission line interconnections, and the circuit terminations have to be matched to this impedance. Several references and tools are available to calculate the geometry for a required impedance or vice versa, for instance the CVEL PCB Trace Impedance Calculator.

4-layer

The four-layer construction allows you to devote two layers to power and 0V planes and two to component placement and tracking. It's only permissible to put tracking on the plane layers if you know that doing so won't compromise the continuity of the plane where it matters. A continuous 0V plane is the first priority, so any tracking that has to run internally should prefer the power plane layer.

The main EMC purpose of a 0V plane is to provide a low-impedance ground and power return path to minimize induced ground noise. Shielding effects on signal tracks are secondary. Putting power and ground planes outside the signal planes (D in the diagram) on 4-layer boards will only be a significant advantage if E-field shielding of the tracks is necessary, and this will in any case be compromised by the unavoidable fields from the components. It greatly reduces the beneficial effect of proximity of the planes. It's not recommended except for special applications with few or no components, such as low performance backplanes.

Therefore the only real decision to make is the separation distance between the layers. The simplest is equal distances (A) which is normally adequate for general purpose designs such as single-chip microcontrollers or non-digital circuits. If you know that the power planes will be carrying a large amount of high frequency noise and you want to minimise the effect of this source of interference, then put the two plane layers close together in the centre of the stack (B). But this will increase the separation of the planes from the outer layers and hence increase the noisiness and susceptibility of the signal tracks. So the alternative is to put the planes closer to the outside of the stack to give better signal integrity of the signal tracks (C). But this increases the plane-to-plane impedance and reduces the planes' decoupling effectiveness. The choice therefore hinges on the balance to be struck between these two aspects.

6-layer

In multilayer (>4) configurations, the most important aspect is that every high-speed signal layer should be adjacent to a ground or power plane layer. As always, power and ground planes should be on adjacent layers and as close as possible, to take advantage of the interlayer capacitance for high frequency decoupling. The capacitance can be increased by using high-K dielectric material for the inter-plane separator, though this also has the effect of lowering the plane resonance frequencies. Critical tracks should be routed adjacent to ground rather than power planes, for preference. Such tracks (typically carrying high di/dt signals such as clocks) should also not jump through vias from one ground reference layer to another, unless the ground layers are tied together with vias at that point.

A six-layer construction with equidistant layer separation (A) offers relatively few advantages over four layers, except extra layers for routing. However, if you can accept an asymmetrical stack and one less routing layer, it is possible to achieve very good power plane decoupling alongside good high speed routing (on different layers - B). Putting the power and ground planes next to the component placement minimizes the via inductance for decoupling purposes. It may be necessary to consider copper balance more carefully with this arrangement.

8-layer

8-layer stacks are the minimum if you want both good EMC performance and double sided assembly, with high performance devices on one or both sides. The most effective arrangements are as shown in (A) for symmetrical but non-equidistant spacing, or (B) for equidistant spacing. Putting the plane layers close together on each side and near the surface allows for excellent decoupling, even of multiple overlaid power planes. The power and 0V plane layers can be swapped depending on which signal layer you want to be next to the 0V plane, which is preferable for the best signal integrity. A signal track that runs against a power plane is fine if it remains against the same plane for its whole length, but you should be careful of signal tracks that have to cross power plane boundaries - these shouldn't be characterised as transmission lines.

If you particularly need high-speed signal layers but only one power plane layer, then the arrangement of (C) gives double-sided track routing and placement at the expense of increased inductance of the decoupling vias.

Boards of more than 8 layers can maintain the arrangement of (A) or (B) with outer layers devoted to power/0V plane pairs and further internal layer sets devoted to high speed and/or constant impedance signal routing, with 0V planes as necessary.

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