Digital circuits tend to be more susceptible to transient disturbances, since they are state machines whose state can be disrupted by a transient duration of no more than a few nanoseconds. Often the coincidence of an incoming transient with a particular period in the operating cycle, typically a clock transition, will result in a much higher degree of susceptibility than at other periods. As a result, you have to apply a statistically large number of transients to be sure of having discovered all the relevant susceptibilities.

As a first defence, lay out the circuit to keep ground interference currents away from the logic circuits. Secondly, filter the I/O leads or isolate them, to define a preferential safe current path for interference. Radiated RF fields that generate differential-mode voltages internally are dealt with in the same way as differential RF emissions, by minimizing circuit loop area.

The best logic device for immunity will be one which has a high noise threshold and a low bandwidth – the faster its operation, the more susceptible to short pulses and RF it will be. Use synchronous design, and try to avoid edge-triggered data inputs wherever possible. All such inputs, and particularly system or chip-level reset input pins, should be regarded as extra-sensitive. This means that their tracks must benefit from the best protection by running adjacent to the ground plane along their whole length, and will normally be protected also by low-value RC filters close to the input. Transients coupled via the power rail can be equally disruptive - this means that decoupling of the supplies is as important for immunity as it is for emissions.

RF interference

When a circuit is subject to RF fields or common mode injected RF stress, localised E- and H-fields induce voltages and currents into each logic node in the circuit. The level of interference voltage at each input will be a function of the circuit loop and node areas, and the circuit impedances. Minimizing the signal/0V loop geometry of each node, and choosing low output impedance drivers, will reduce the induced noise voltages, and using devices with a high static and dynamic noise immunity will maximize the threshold at which interference effects occur.

The first effect of RFI to be noticed on dynamically active logic circuits is timing jitter at the transitions. If the circuit timing is critical then this itself can cause malfunction. As the RF level increases then actual spurious logic level transitions occur and these will propagate through the circuit if the logic response speed is high enough. Often, different thresholds are found for logic 0 and logic 1 effects because of the different driver output impedances. Edge-triggered circuits will be particularly sensitive as these will latch asynchronously - they do not depend on coincidence with a clock edge. Polarity of the quiescent state is also relevant, as (for example) active high transition clock inputs are far more sensitive when held at logic 0 than when at logic 1.

ESD and transients

A fast-rising current pulse and its associated magnetic field travelling across a printed circuit board will induce a voltage differential across the inductive component of each PCB track, as with RF disturbances. The effect of this is that a differential noise spike will appear in series with the voltage at each circuit node; the amplitude of the noise spike will depend on the coupling inductance of that circuit (large, widely spaced signal/return loops will induce high voltages) and the impedance at the susceptible device input (the lower the input impedance, the lower the noise voltage).

It will be invisible to digital circuits if its amplitude is less than the circuit’s operating dynamic noise margin. This is the threshold below which very short input pulses do not affect the output state; it becomes higher than the static noise margin as the pulse width gets shorter. This noise margin will be different for logic high and low levels and therefore susceptibility to opposite polarities of ESD may vary – although if the transient excites spurious resonances in the layout or circuit, the resultant ringing waveform can have approximately equal positive and negative components. If the voltage exceeds the noise margin – and a 10A/ns rising edge can induce 2V into a 1cm² loop area, 10cm away – then synchronous logic circuits will suffer mis-clocking, and the coincidence of data/address transients with active clock edges will cause false data to propagate through the system.

The watchdog

However good the circuit’s immunity, there will always be a disturbance that will defeat it. Every microprocessor should include a watchdog.

The most serious result of a transient corruption is that the processor program counter, stack or address register is upset, so that it starts interpreting data or empty memory as valid instructions. This causes the processor to enter an endless loop, either doing nothing or performing a few meaningless operations. It will appear to be catatonic, in a state of "dynamic halt".

A watchdog guards against this by requiring the processor to execute a specific simple operation regularly, regardless of what else it is doing, on pain of consequent reset. A timer whose output is linked to the RESET input is itself being constantly retriggered by the operation the processor performs, normally writing to a spare output port. If the timer does not receive a "kick" from the output port for more than its timeout period, its output goes low and forces the microprocessor into reset.

If the interference transient recurs while the processor is re-booting it would be possible for a second crash to occur before the watchdog software had been re-enabled. For this reason it is important that the watchdog hardware should be capable of repeatedly restarting the processor until it succeeds. Also, the watchdog output should always be taken to the processor’s reset input in order to ensure a correct re-start: other inputs such as interrupts can't guarantee a proper recovery from every fault state. If you have to distinguish between a watchdog re-start and a power on reset, external circuitry should be provided to achieve this.

Defensive software

It's easy to think that the software within the processor is never affected by interference - a clean, disturbance-free virtual environment. But this is wishful thinking. Corruption to program control and data can and does occur; but some precautions against interference can be taken in the software itself. Techniques include:

type-check and range-check all input data

sample input data several times and either average it, for analogue data, or validate it, for digital data

incorporate parity checking and data checksums in all data transmission

protect data blocks in volatile memory with error detecting and correcting algorithms; implement write locking on non-volatile memory

wherever possible rely on level- rather than edge-triggered interrupts; monitor the stack pointer for overflow

periodically re-initialize programmable interface devices, especially I/O port registers

incorporate token passing in subroutine calls

Some means of disabling software error-checking is necessary during development, when testing equipment against interference, as otherwise you can't assess the true performance of the hardware design.

Of course, not all microprocessor faults are due to interference. Other sources are intermittent connections, marginal hardware design, software bugs, meta-stability of asynchronous circuits, and so on; but these should be discovered and dealt with in the development stage. Using simple transient generators (ESD and EFT/B simulators) can help to identify EMC-related weaknesses at this stage as well.

Click here for Questions